View SRI512-A5T1GE_1812055.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

july 2009 doc id 13263 rev 5 1/47 1 sri512 13.56 mhz short-range contactless memory chip with 512-bit eeprom and anticollision functions features iso 14443-2 type b air interface compliant iso 14443-3 type b frame format compliant 13.56 mhz carrier frequency 847 khz subcarrier frequency 106 kbit/second data transfer 8 bit chip_id based anticollision system 2 count-down binary counters with automated antitearing protection 64-bit unique identifier 512-bit eeprom with wr ite protect feature read_block and write_block (32 bits) internal tuning capacitor 1million erase/write cycles 40-year data retention self-timed programming cycle 5 ms typical programming time ?unsawn wafer ? bumped and sawn wafer www.st.com
contents sri512 2/47 doc id 13263 rev 5 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 ac1, ac0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 input data transfer from the reader to the sri512 (request frame) . . . . . . 9 3.1.1 character transmission format for request frame . . . . . . . . . . . . . . . . . . 9 3.1.2 request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1.3 request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 output data transfer from the sri512 to the reader (answer frame) . . . . 11 3.2.1 character transmission format for answer frame . . . . . . . . . . . . . . . . . . 11 3.2.2 answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2.3 answer end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.3 transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 crc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 resettable otp area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.2 32-bit binary counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.3 eeprom area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 system area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4.1 otp_lock_reg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4.2 fixed chip_id (option) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5 sri512 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 sri512 states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 ready state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.3 inventory state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4 selected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.5 deselected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
sri512 contents doc id 13263 rev 5 3/47 6.6 deactivated state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7 anticollision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.1 description of an anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . 26 8 sri512 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.1 initiate() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.2 pcall16() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.3 slot_marker(sn) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.4 select(chip_id) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.5 completion() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.6 reset_to_inventory() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.7 read_block(addr) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.8 write_block (addr, data) command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.9 get_uid() command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.10 power-on state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 appendix a iso 14443 type b crc calculation . . . . . . . . . . . . . . . . . . . . . . . . . 43 appendix b sri512 command brie f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
list of tables sri512 4/47 doc id 13263 rev 5 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3. sri512 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4. standard anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 5. command code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 7. operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 8. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 9. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 10. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 11. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
sri512 list of figures doc id 13263 rev 5 5/47 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 2. die floor plan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. 10% ask modulation of the received wave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4. sri512 request frame character format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. request start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 6. request end of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 7. wave transmitted using bpsk subc arrier modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 8. answer start of frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9. answer end of frame. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 10. example of a complete transmission frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11. crc transmission rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12. resettable otp area (addresses 0 to 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 13. write_block update in standard mode (binary format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 14. write_block update in reload mode (binary format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 15. binary counter (addresses 5 to 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 16. count down example (binary format) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 17. eeprom (addresses 7 to 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 18. system area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 19. state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 20. sri512 chip_id description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 21. description of a po ssible anticollision sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 22. example of an anticollision sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 23. initiate request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 24. initiate response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 25. initiate frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 26. pcall16 request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 27. pcall16 response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 28. pcall16 frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 29. slot_marker request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 30. slot_marker response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 31. slot_marker frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 32. select request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 33. select response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 34. select frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 35. completion request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 36. completion response format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 37. completion frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 38. reset_to_inventory request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 39. reset_to_inventory response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 40. reset_to_inventory frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . 34 figure 41. read_block request format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 42. read_block response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 43. read_block frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 44. write_block request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 45. write_block response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 46. write_block frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 47. get_uid request format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 48. get_uid response format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
list of figures sri512 6/47 doc id 13263 rev 5 figure 49. 64-bit unique identifier of the sri512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 50. get_uid frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 51. sri512 synchronous timing, transmit and receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 52. initiate frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 53. pcall16 frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 54. slot_marker frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 55. select frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 56. completion frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 57. reset_to_inventory frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . 45 figure 58. read_block frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 59. write_block frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 60. get_uid frame exchange between reader and sri512 . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
sri512 description doc id 13263 rev 5 7/47 1 description the sri512 is a contactless memory, powered by an externally transmitted radio wave. it contains a 512-bit user eeprom fabricated with stmicroelectronics cmos technology. the memory is organized as 16 blocks of 32 bits. the sri512 is accessed via the 13.56 mhz carrier. incoming data are demodulated and decoded from the received amplitude shift keying (ask) modulation signal and outgoing data ar e generated by load variation using bit phase shift keying (bpsk) coding of a 847 khz subcarrier. the received ask wave is 10% modulated. th e data transfer rate between the sri512 and t he reader is 106 kbit/s in both reception and emission modes. the sri512 follows the iso 14443-2 type b recommendation for the radio-frequency power and signal interface. figure 1. logic diagram the sri512 is specifically designed for s hort range applications that need re-usable products. the sri512 includes an ant icollision mechanism that allows it to detect and select tags present at the same time within range of the reader. using the stmicroelectronics single chip coupler, crx14, it is easy to design a reader and build a contactless system. table 1. signal names signal name description ac1 antenna coil ac0 antenna coil ai10795 ac1 sri512 ac0 power supply regulator bpsk load modulator ask demodulator 512-bit user eeprom
signal description sri512 8/47 doc id 13263 rev 5 the sri512 contactless eeprom can be randoml y read and written in block mode (each block containing 32 bits). the instruction set includes the following nine commands: read_block write_block initiate pcall16 slot_marker select completion reset_to_inventory get_uid the sri512 memory is organized in three areas, as described in ta b l e 3 . the first area is a resettable otp (one-time programmable) area in which bits can only be switched from 1 to 0. using a special command, it is possible to erase all bits of this area to 1. the second area provides two 32-bit binary counters that can only be decremented from ffff ffffh to 0000 0000h, and gives a capaci ty of 4,294,967,296 units per counter. the last area is the eeprom memo ry. it is accessible by bloc k of 32 bits and includes an auto-erase cycle during each write_block command. figure 2. die floor plan 2 signal description 2.1 ac1, ac0 the pads for the antenna coil. ac1 and ac0 must be directly bonded to the antenna. ai09055 ac1 ac0
sri512 data transfer doc id 13263 rev 5 9/47 3 data transfer 3.1 input data transfer from the reader to the sri512 (request frame) the reader must generate a 13.56 mhz sinusoidal carrier frequency at its antenna, with enough energy to ?remote-power? the memory. the energy received at the sri512?s antenna is transformed into a supply voltage by a regulator, and into data bits by the ask demodulator. for the sri512 to decode correctly the information it receives, the reader must 10% amplitude-modulate the 13.56 mhz wave before sending it to the sri512. this is represented in figure 3 . the data transfer rate is 106 kbits/s. figure 3. 10% ask modulation of the received wave 3.1.1 character transmission format for request frame the sri512 transmits and receives data bytes as 10-bit characters, with the least significant bit (b 0 ) transmitted first, as shown in figure 4 . each bit duration, an etu (elementary time unit), is equal to 9.44 s (1/106 khz). these characters, framed by a start of frame (sof) and an end of frame (eof), are put together to form a command frame as shown in figure 10 . a frame includes an sof, commands, addresses, data, a crc and an eof as defined in the iso 14443-3 type b standard. if an error is detected during data transfer, the sri512 does not execute the command, but it does not generate an error frame. figure 4. sri512 request frame character format data bit to transmit to the 10% ask modulation of the 13.56mhz wave, generated by the reader transfer time for one data bit is 1/106 khz sri512 ai10796 ai07664 1 etu start "0" stop "1" msb lsb information byte b0 b1 b2 b3 b4 b5 b6 b7 b8 b9
data transfer sri512 10/47 doc id 13263 rev 5 3.1.2 request start of frame the sof described in figure 5 is composed of: one falling edge, followed by 10 etus at logic-0, followed by a single rising edge, followed by at least 2 etus (and at most 3) at logic-1. figure 5. request start of frame 3.1.3 request end of frame the eof shown in figure 6 is composed of: one falling edge, followed by 10 etus at logic-0, followed by a single rising edge. figure 6. request end of frame table 2. bit description bit description value b 0 start bit used to synchronize the transmission b 0 = 0 b 1 to b 8 information byte (command, address or data) the information byte is sent with the least significant bit first b 9 stop bit used to indicate the end of a character b 9 = 1 ai07665 etu b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 000000000011 ai07666 etu b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 0000000000
sri512 data transfer doc id 13263 rev 5 11/47 3.2 output data transfer from the sri512 to the reader (answer frame) the data bits issued by the sri512 use back- scattering. back-scattering is obtained by modifying the sri512 current consumption at the antenna (load modulation). the load modulation causes a variation at the reader antenna by inductive coupling. with appropriate detector circuitry, the reader is able to pick up information from the sri512. to improve load- modulation detection, data is transmitted using a bpsk en coded, 847 khz subcarrier frequency ? s as shown in figure 7 , and as specified in the iso 14443-2 type b standard. figure 7. wave transmitted using bpsk subcarrier modulation 3.2.1 character transmission format for answer frame the character format is the same as for input data transfer ( figure 4 ). the transmitted frames are made up of an sof, data, a crc and an eof ( figure 10 ). as with an input data transfer, if an error occurs, the reader does not issue an error code to the sri512, but it should be able to detect it and manage the situation. the data transfer rate is 106 kbits/second. 3.2.2 answer start of frame the sof described in figure 8 is composed of: followed by 10 etus at logic-0 followed by 2 etus at logic-1 figure 8. answer start of frame or ai10797 data bit to be transmitted to the reader 847khz bpsk modulation generated by the sri512 bpsk modulation at 847khz during a one-bit data transfer time (1/106khz) ai07665 etu b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 000000000011
data transfer sri512 12/47 doc id 13263 rev 5 3.2.3 answer end of frame the eof shown in figure 9 is composed of: followed by 10 etus at logic-0, followed by 2 etus at logic-1. figure 9. answer end of frame 3.3 transmission frame between the request data transfer and the answer data transfer, all ask and bpsk modulations are suspended for a minimum time of t 0 = 128/? s . this delay allows the reader to switch from transmission to reception mode. it is repeated after each frame. after t 0 , the 13.56 mhz carrier frequency is modulated by the sri512 at 847 khz for a period of t 1 =128/? s to allow the reader to synchronize. after t 1 , the first phase transition generated by the sri512 forms the start bit (?0?) of the answer sof. after the falling edge of the answer eof, the reader waits a minimum time, t 2 , before sending a new request frame to the sri512. figure 10. example of a complete transmission frame ai07665 etu b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 000000000011 12 bits 10 bits sync 128/fs 128/fs f s =847.5khz t dr t 0 t 1 sof cmd data crc crc eof 10 bits 10 bits 10 bits 10 bits 12 bits 10 bits 10 bits 10 bits data crc crc sof eof 12 bits sof t 2 ai10798 input data transfer using ask output data transfer using bpsk sent by the reader sent by the sri512 at 106kb/s
sri512 data transfer doc id 13263 rev 5 13/47 3.4 crc the 16-bit crc used by the sri512 is generated in compliance with the iso14443 type b recommendation. for further information, please see appendix a . the initial register contents are all 1?s: ffffh. the two-byte crc is present in every request and in every answer frame, before the eof. the crc is calculated on all the bytes between sof (not included) and the crc field. upon reception of a request from a reader, the sri512 verifies that the crc value is valid. if it is invalid, the sri512 discards the frame and does not answer the reader. upon reception of an answer from the sri512, the reader should verify the validity of the crc. in case of error, the ac tions to be taken are the re ader designer?s responsibility. the crc is transmitted with the least signific ant byte first and each byte is transmitted with the least significant bit first. figure 11. crc tr ansmission rules crc 16 (8 bits) crc 16 (8 bits) lsbit msbit lsbit msbit lsbyte msbyte ai07667
memory mapping sri512 14/47 doc id 13263 rev 5 4 memory mapping the sri512 is organized as 16 blocks of 32 bits as shown in ta b l e 3 . all blocks are accessible by the read_block command. depending on the write access, they can be updated by the write_block command. a write_block updates all the 32 bits of the block. table 3. sri512 memory mapping block addr msb 32-bit block lsb b 31 b 16 b 15 b 14 b 8 b 7 b 0 description 0 32 bits boolean area resettable otp bits 1 32 bits boolean area 2 32 bits boolean area 3 32 bits boolean area 4 32 bits boolean area 5 32 bits binary counter count down counter 6 32 bits binary counter 7user area lockable eeprom 8user area 9user area 10 user area 11 user area 12 user area 13 user area 14 user area 15 user area 255 otp_lock_reg 0 st reserved fixed chip_id (option) system otp bits uid0 64 bits uid area rom uid1
sri512 memory mapping doc id 13263 rev 5 15/47 4.1 resettable otp area this area contains five individual 32-bit boolean words (see figure 12 for a map of the area). a write_block command will not erase the pr evious contents of the block as the write cycle is not preceded by an auto-erase cycle. this feature can be used to reset selected bits from 1 to 0. all bits previously at 0 remain unchanged. when the 32 bits of a block are all at 0, the block is empty, and cannot be updated any more. see figure 13 and figure 14 for examples of the result of the write_block command in the resettable otp area. figure 12. resettable otp area (addresses 0 to 4) figure 13. write_block update in standard mode (binary format) the five 32-bit blocks making up the resettable otp area can be erased in one go by adding an auto-erase cycle to the write_bl ock command. an auto-erase cycle is added each time the sri512 detects a reload command. the reload command is implemented through a specific update of the 32-bit binary counter located at block address 6 (see section 4.2: 32-bit binary counters for details). block address msb b31 32-bit block b16 b15 b14 b8 b7 lsb b0 description resettable otp bit 0 1 2 3 4 32-bit boolean area 32-bit boolean area 32-bit boolean area 32-bit boolean area 32-bit boolean area ai12381 ai07658 1 ... 1 1 01011 11 1 0 11 1 ... 1 0 01011 00 1 1 11 1 ... 1 0 01011 00 1 0 11 previous data stored in block data to be written new data stored in block b31 b0
memory mapping sri512 16/47 doc id 13263 rev 5 figure 14. write_block update in reload mode (binary format) 4.2 32-bit binary counters the two 32-bit binary counters located at block addresses 5 and 6, respectively, are used to count down from 2 32 (4096 million) to 0. t he sri512 uses dedicated logic that only allows the update of a counter if the new value is lower than the previous one. this feature allows the application to count down by steps of 1 or more. the initial va lue is ffff fffeh in counter 5 and, ffff ffffh in counter 6. when the value displayed is 0000 0000h, the counter is empty and cannot be reloaded. the counter is updated by issuing the write_block command to block address 5 or 6, depending on which counter is to be updated. the write_block command writes the new 32-bit value to the counter block address. figure 16 shows examples of how the counters operate. the counter programming cycles are protected by automated antitearing logic. this function allows the counter value to be protected in case of power down within the programming cycle. in case of power down, the counter value is not updated and the previous value continues to be stored. blocks 5 and 6 can be write-protected using the otp_lock_reg bits (block 255). once a block has been protected, its contents cannot be modified. a protected counter block behaves like a rom block. figure 15. binary counter (addresses 5 to 6) ai07659 1...11 0 1011 11 1 0 11 1...11 1 1011 00 1 1 11 1...11 1 1011 00 1 1 11 previous data stored in block data to be written new data stored in block b31 b0 block address msb 32-bit block lsb description count down counter 5 6 32-bit binary counter 32-bit binary counter ai12384b b31 b16 b15 b14 b8 b7 b0
sri512 memory mapping doc id 13263 rev 5 17/47 figure 16. count down example (binary format) the counter with block address 6 controls the reload command used to reset the resettable otp area (addresses 0 to 4). bits b 31 to b 21 act as an 11-bit reload counter; whenever one of these 11 bits is updated, the sri512 detects the change and adds an erase cycle to the write_block command for locations 0 to 4 (see section 4.1: resettable otp area ). the erase cycle remains active until a power-off or a select command is issued. the sri512?s resettable otp area can be reloaded up to 2,047 times (2 11 -1). ai07661 1...1111111111111 1...111111111111 0 1...11111111111 01 initial data 1-unit decrement 1-unit decrement b31 b0 1...11111111111 00 1...111111111 0100 1...111111111 1000 1-unit decrement 8-unit decrement increment not allowed
memory mapping sri512 18/47 doc id 13263 rev 5 4.3 eeprom area the 9 blocks between addresses 7 and 15 are eeprom blocks of 32 bits each (36 bytes in total). (see figure 17 for a map of the area.) these blocks can be accessed using the read_block and write_block commands. the write_block command for the eeprom area always includes an auto-erase cycle prior to the write cycle. blocks 7 to 15 can be write-protected. write access is controlled by the 9 bits of the otp_lock_reg located at block address 255 (see section 4.4.1: otp_lock_reg for details). once protected, these blocks (7 to 15) cannot be unprotected figure 17. eeprom (addresses 7 to 15) block address msb 32-bit block lsb description lockable eeprom 7 8 9 10 11 user area user area user area user area user area ai12383b 13 14 15 user area user area user area 12 user area b31 b16 b15 b14 b8 b7 b0
sri512 memory mapping doc id 13263 rev 5 19/47 4.4 system area this area is used to modify the settings of the sri512. it contains 3 registers: otp_lock_reg, fixed chip_id and st reserved. see figure 18 for a map of this area. a write_block command in this area will not eras e the previous contents. selected bits can thus be set from 1 to 0. all bits previously at 0 remain unchanged. once all the 32 bits of a block are at 0, the block is empty and cannot be updated any more. figure 18. system area 4.4.1 otp_lock_reg the 16 bits, b31 to b16, of the system area (block address 255) are used as otp_lock_reg bits in the sri512. they control the write access to the 16 blocks 0 to 15 as follows: when b16 is at 0, block 0 is write-protected when b17 is at 0, block 1 is write-protected when b18 is at 0, block 2 is write-protected when b19 is at 0, block 3 is write-protected when b20 is at 0, block 4 is write-protected when b21 is at 0, block 5 is write-protected when b22 is at 0, block 6 is write-protected when b23 is at 0, block 7 is write-protected when b24 is at 0, block 8 is write-protected when b25 is at 0, block 9 is write-protected when b26 is at 0, block 10 is write-protected when b27 is at 0, block 11 is write-protected when b28 is at 0, block 12 is write-protected when b29 is at 0, block 13 is write-protected when b30 is at 0, block 14 is write-protected when b31 is at 0, block 15 is write-protected. the otp_lock_reg bits cannot be erased. once write-protected, the blocks behave like rom blocks and cannot be unprotected. after any modification of the otp_lock_reg bits, it is necessary to send a select command with a valid chip_id to the sri512 in order to load the block write protection into the logic. block address 255 msb 32-bit block lsb description otp otp_lock_reg st reserved fixed chip_id (option) ai12374b 0 b31 b16 b15 b14 b8 b7 b0
memory mapping sri512 20/47 doc id 13263 rev 5 4.4.2 fixed chip_id (option) the sri512 is provided with an anticollision feat ure based on a random 8-bit chip_id. prior to selecting an sri512, an antico llision sequence has to be run to search for the chip_id of the sri512. this is a very flexible feature, however the searching loop requires time to run. for some applications, much time could be saved by knowing the value of the sri512 chip_id beforehand, so that the sri512 can be identified and selected directly without having to run an anticollision sequence. this is why the sr i512 was designed with an optional mask setting used to program a fixed 8-bit chip_id to bits b 7 to b 0 of the system area. when the fixed chip_id option is used, the random chip_id function is disabled.
sri512 sri512 operation doc id 13263 rev 5 21/47 5 sri512 operation all commands, data and crc are transmitted to the sri512 as 10-bit characters using ask modulation. the start bit of the 10 bits, b 0 , is sent first. the command frame received by the sri512 at the antenna is demodulated by the 10% ask demodulator, and decoded by the internal logic. prior to any operation, the sri512 must have been selected by a select command. each frame transmitted to the sri512 must start with a start of frame, followed by one or more data characters, two crc bytes and the final end of frame. when an invalid frame is decoded by the sri512 (wrong command or crc error), the memory does not return any error code. when a valid frame is received, the sri512 may have to return data to the reader. in this case, data is returned using bpsk encoding, in the form of 10-b it characters framed by an sof and an eof. the transfer is ended by the sri512 sending the 2 crc bytes and the eof.
sri512 states sri512 22/47 doc id 13263 rev 5 6 sri512 states the sri512 can be switched into different states. depending on the current state of the sri512, its logic will only answ er to specific commands. th ese states are mainly used during the anticollision sequence, to identify and to access the sri512 in a very short time. the sri512 provides 6 different states, as de scribed in the following paragraphs and in figure 19 . 6.1 power-off state the sri512 is in power-off state when the electromagnetic field around the tag is not strong enough. in this state, the sri512 does not respond to any command. 6.2 ready state when the electromagnetic field is strong enough, the sri512 enters the ready state. after power-up, the chip_id is init ialized with a random value. the whole logic is reset and remains in this state until an initiate() command is iss ued. any other command will be ignored by the sri512. 6.3 inventory state the sri512 switches from the ready to the inventory state after an initiate() command has been issued. in inventory state, the sri5 12 will respond to any anticollision commands: initiate(), pcall16() and slot_marke r(), and then remain in the in ventory state. it will switch to the selected state after a select(chip_id) command is issued, if the chip_id in the command matches its own. if not, it will remain in inventory state. 6.4 selected state in selected state, the sri512 is active and responds to all read_block(), write_block(), and get_uid() commands. when an sri512 has entered the selected state, it no longer responds to anticollision command s. so that the reader can ac cess another tag, the sri512 can be switched to the desele cted state by sending a select(chip_id2) with a chip_id that does not match its own, or it can be placed in deactivated state by issuing a completion() command. only one sri512 can be in selected state at a time. 6.5 deselected state once the sri512 is in deselected state, only a select(chip_id) command with a chip_id matching its own can switch it back to selected state. all other commands are ignored. 6.6 deactivated state when in this state, the sri512 can only be turned off. all commands are ignored.
sri512 sri512 states doc id 13263 rev 5 23/47 figure 19. state transition diagram power-off ready on field out of field chip_id 8bits = rnd inventory initiate() initiate() or pcall16() or slot_marker(sn) or select(wrong chip_id) out of field select(chip_id) selected out of field deselected deactivated select( chip_id) select(chip_id) completion() out of field out of field read_block() write_block() get_uid() reset_to_inventory() select(chip_id) ai10794b
anticollision sri512 24/47 doc id 13263 rev 5 7 anticollision the sri512 provides an anticollis ion mechanism that searches for the chip_id of each device that is present in the reader field range. when known, the chip_id is used to select an sri512 individually, and access its memo ry. the anticollision se quence is managed by the reader through a set of commands described in section 5: sri512 operation : initiate() pcall16() slot_marker(). the reader is the master of the communication with one or more sri512 device(s). it initiates the tag communication activity by issuing an initiate(), pcall16() or slot_marker() command to prompt the sri512 to answer. du ring the anticollision sequence, it might happen that two or more sri512 devices resp ond simultaneously, so causing a collision. the command set allows the reader to handle the sequence, to separate sri512 transmissions into diff erent time slots. once the antic ollision sequence has completed, sri512 communication is fully under the control of the reader, allowing only one sri512 to transmit at a time. the anticollision scheme is bas ed on the definition of time slots durin g which the sri512 devices are invited to answer with minimum identification data: the chip_id. the number of slots is fixed at 16 for the pcall16() command. for the initiate() command, there is no slot and the sri512 answers after the command is issued. sri512 devices are allowed to answer only once during the anticollision sequence. consequent ly, even if there are several sri512 devices present in the reader field, there will probably be a sl ot in which only one sri512 answers, allowing the reader to capture its chip_id. using the chip_id, the reader can then establish a communication channel with the identified sri512. the purpose of the anticollision sequence is to allow the re ader to select on e sri512 at a time. the sri512 is given an 8-bit chip_id value used by the reader to select only one among up to 256 tags present within its field range. the chip_id is initialized with a random value during the ready state, or after an initiate() command in the inventory state. the four least significant bits (b 0 to b 3 ) of the chip_id are also known as the chip_slot_number. this 4-bit value is used by the pcall16() and slot_marker() commands during the anticollision seque nce in the inventory state. figure 20. sri512 chip_id description each time the sri512 receives a pcall16() command, the chip_slot_number is given a new 4-bit random value. if the new value is 0000 b , the sri512 returns its whole 8-bit chip_id in its answer to the pcall16() command. the pcall16() command is also used to define the slot number 0 of the anticollision sequence. when the sri512 re ceives the slot_marker(sn) command, it compares its chip_slot_number with the slot_number parameter (sn). if they match, the sri512 returns its chip_id as a response to the command. if they do not, the sri512 does not answer. the slot_marker(sn) command is used to define all the anticollision slot numbers from 1 to 15. ai07668 b7 b6 b5 b4 b3 b2 b1 b0 8-bit chip_id b0 to b3: chip_slot_number
sri512 anticollision doc id 13263 rev 5 25/47 figure 21. description of a possible anticollision sequence 1. the value x in the answer chip_id means a random hexadecimal char acter from 0 to f. slot 0 slot 1 slot 2 slot n slot 15 <><> < > reader sri devices s o f e o f <-> <-> <-> <-> < > <-> <-> <-> timing t 0 + t 1 t 2 t 0 + t 1 t 2 t 3 t 0 + t 1 comment no collision time > ai10799 <> collision no answer t 2 no collision t 2 ... answer chip_id x1h e o f e o f e o f answer chip_id x0h answer chip_id xfh s o f s o f s o f s o f s o f s o f e o f e o f e o f e o f s o f s o f e o f pcall 16 request slot marker (1) slot marker (2) answer chip_id x1h slot marker (15) ...
anticollision sri512 26/47 doc id 13263 rev 5 7.1 description of an anticollision sequence the anticollision sequence is initiated by the initiate() command which triggers all the sri512 devices that are present in the reader field range, and that are in inventory state. only sri512 devices in inventory state will re spond to the pcall16( ) and slot_marker(sn) anticollision commands. a new sri512 introduced in the field range during the anticollision sequ ence will not be taken into account as it will not respond to the pcall16() or slot_marker(sn) command (ready state). to be considered during the anticollision sequence, it must have received the initiate() command and entered the inventory state. ta bl e 4 shows the elements of a standa rd anticollision sequence. (see figure 22 for an example.) after each slot_marker() command, there may be several, one or no answers from the sri512 devices. the reader must handle all the cases and store all the chip_ids, correctly decoded. at the end of the anticollision sequence, after slot_marker(15), the reader can start working with one sri512 by issuing a select() command containing the desired chip_id. if a collision is detected during th e anticollision sequence, the reader has to generate a new sequence in order to identify all unidentified sri512 devices in the field. the anticollision sequence can st op when all sri512 device s have been identified. table 4. standard anticollision sequence step 1 init: send initiate(). ? if no answer is detected, go to step1. ? if only 1 answer is detected, select and access the sri512. after accessing the sri512, deselect the tag and go to step1. ? if a collision (many answers) is detected, go to step2. step 2 slot 0 send pcall16(). ? if no answer or collision is detected, go to step3. ? if 1 answer is detected, store the ch ip_id, send select() and go to step3. step 3 slot 1 send slot_marker(1). ? if no answer or collision is detected, go to step4. ? if 1 answer is detected, store the ch ip_id, send select() and go to step4. step 4 slot 2 send slot_marker(2). ? if no answer or collision is detected, go to step5. ? if 1 answer is detected, store the ch ip_id, send select() and go to step5. step n slop n send slot_marker(3 up to 14) ... ? if no answer or collision is detected, go to stepn+1. ? if 1 answer is detected, store the chi p_id, send select() and go to stepn+1. step 17 slot 15 send slot_marker(15). ? if no answer or collision is detected, go to step18. ? if 1 answer is detected, store the ch ip_id, send select() and go to step18. step 18 all the slots have been generated and the chip_id values should be stored into the reader memory. issue the select(chip_id) command and access each identified sri512 one by one. after accessing each sri512, switch them into deselected or deactivated state, depending on the application needs. ? if collisions were detected between step2 and step17, go to step2. ? if no collision was detected between step2 and step17, go to step1.
sri512 anticollision doc id 13263 rev 5 27/47 figure 22. example of an anticollision sequence command tag 1 chip_id tag 2 chip_id tag 3 chip_id tag 4 chip_id tag 5 chip_id tag 6 chip_id tag 7 chip_id tag 8 chip_id comments ready state 28h 75h 40h 01h 02h feh a9h 7ch each tag gets a random chip_id initiate () 40h 13h 3fh 4ah 50h 48h 52h 7ch each tag get a new random chip_id all tags answer: collisions 45h 12h 30h 43h 55h 43h 53h 73h all chip_slot_numbers get a new random value pcall16() 30h slot0: only one answer 30h tag3 is identified select(30h) slot_marker(1) slot1: no answer slot_marker(2) slot2: only one answer 12h 12h tag2 is identified select(12h) slot_marker(3) slot3: collisions slot_marker(4) slot4: no answer 43h 43h 53h 73h slot_marker(5) slot5: collisions slot_marker(6) slot6: no answer 45h 55h slot_marker(n) slotn: no answer slot_marker(f) slotf: no answer 40h 41h 53h 42h 50h 74h all chip_slot_numbers get a new random value pcall16() 40h slot0: collisions slot_marker(1) slot1: only one answer slot_marker(2) slot2: only one answer 42h tag6 is identified select(42h) slot_marker(3) slot3: only one answer select(53h) tag5 is identified 53h slot_marker(4) slot4: only one answer select(74h) tag8 is identified 74h slot_marker(n) slotn: no answer 50h 41h tag4 is identified select(41h) 41h 42h 53h 74h 41h 50h all chip_slot_numbers get a new random value pcall16() slot0: only one answer 50h tag7 is identified select(50h) slot_marker(1) slot1: only one answer but already found for tag4 slot_marker(n) slotn: no answer 50h 41h 43h all chip_slot_numbers get a new random value pcall16() slot0: only one answer slot_marker(3) slot3: only one answer 43h tag1 is identified select(43h) 43h all tags are identified ai07669
sri512 commands sri512 28/47 doc id 13263 rev 5 8 sri512 commands see the paragraphs below for a detailed description of the commands available on the sri512. the commands and their hexadecimal codes are summarized in ta bl e 5 . a brief is given in appendix b . table 5. command code hexadecimal code command 06h-00h initiate() 06h-04h pcall16() x6h slot_marker (sn) 08h read_block(addr) 09h write_block(addr, data) 0bh get_uid() 0ch reset_to_inventory 0eh select(chip_id) 0fh completion()
sri512 sri512 commands doc id 13263 rev 5 29/47 8.1 initiate() command command code = 06h - 00h initiate() is used to initiate the anticollision sequence of the sri512. on receiving the initiate() command, all sri512 devices in ready state switch to inventory state, set a new 8- bit chip_id random value, and return their chip_id value. this command is useful when only one sri512 in ready state is present in the reader field range. it speeds up the chip_id search process. the chip_slot_number is not used during initiate() command access. figure 23. initiate request format request parameter: no parameter figure 24. initiate response format response parameter: chip_id of the sri512 figure 25. initiate frame exchange between reader and sri512 sof initiate crc l crc h eof ai07670b 06h 00h 8 bits 8 bits sof chip_id crc l crc h eof ai07671 8 bits 8 bits 8 bits ai10942 reader sri512 sof chip_id crc l crc h eof <-t 0 -> <-t 1 -> sof 06h crc l crc h eof 00h
sri512 commands sri512 30/47 doc id 13263 rev 5 8.2 pcall16() command command code = 06h - 04h the sri512 must be in inventory state to interpret the pcall16() command. on receiving the pcall16() command, the sri512 first generates a new random chip_slot_number value (in the 4 least signific ant bits of the chip_i d). chip_slot_number can take on a value between 0 an 15 (1111 b ). the value is retained until a new pcall16() or initiate() command is issued, or until the sri512 is powered off. the new chip_slot_number value is then compared with the value 0000 b . if they match, the sri512 returns its chip_id value. if not, the sri512 does not send any response. the pcall16() command, used together with the slot_marker() command, allows the reader to search for all the chip_ids when there are more than one sri512 device in inventory state present in the reader field range. figure 26. pcall16 request format request parameter: no parameter figure 27. pcall16 response format response parameter: chip_id of the sri512 figure 28. pcall16 frame exchange between reader and sri512 sof pcall16 crc l crc h eof ai07673b 06h 04h 8 bits 8 bits sof chip_id crc l crc h eof ai07671 8 bits 8 bits 8 bits sof 06h crc l crc h eof ai10943 reader sri512 sof chip_id crc l crc h eof <-t 0 -> <-t 1 -> 04h
sri512 sri512 commands doc id 13263 rev 5 31/47 8.3 slot_marker(sn) command command code = x6h the sri512 must be in inventory state to interpret the slot_marker(sn) command. the slot_marker byte code is divided into two parts: b 3 to b 0 : 4-bit command code with fixed value 6. b 7 to b 4 : 4 bits known as the slot_number (sn). they assume a value between 1 and 15. the value 0 is reserved by the pcall16() command. on receiving the slot_marker() command, the sri512 compares its chip_slot_number value with the slot_number value given in the command code. if they match, the sri512 returns its chip_id value. if not, the sri512 does not send any response. the slot_marker() command, used together with the pcall16() command, allows the reader to search for all the chip_ids when there are more than one sri512 device in inventory state present in the reader field range. figure 29. slot_marker request format request parameter: x: slot number figure 30. slot_marker response format response parameters: chip_id of the sri512 figure 31. slot_marker frame exchange between reader and sri512 sof slot_marker crc l crc h eof ai07675b x6h 8 bits 8 bits sof chip_id crc l crc h eof ai07671 8 bits 8 bits 8 bits sof x6h crc l crc h eof ai10944 reader sri512 sof chip_id crc l crc h eof <-t 0 -> <-t 1 ->
sri512 commands sri512 32/47 doc id 13263 rev 5 8.4 select(chip_id) command command code = 0eh the select() command allows the sri512 to enter the selected state. until this command is issued, the sri512 will not acce pt any other command, except for initiate(), pcall16() and slot_marker(). the select() command returns the 8 bits of the chip_id value. an sri512 in selected state, that receives a select() command with a chip_id t hat does not match its own is automatically switch ed to deselected state. figure 32. select request format request parameter: 8-bit chip_id stored during the anticollision sequence figure 33. select response format response parameters: chip_id of the selected tag. must be equal to the transmitted chip_id figure 34. select frame exchange between reader and sri512 sof select crc l crc h eof ai07677b 0eh 8 bits 8 bits 8 bits chip_id sof chip_id crc l crc h eof ai07671 8 bits 8 bits 8 bits ai10945 reader sri512 sof chip_id crc l crc h eof <-t 0 -> <-t 1 -> sof 0eh crc l crc h eof chip_id
sri512 sri512 commands doc id 13263 rev 5 33/47 8.5 completion() command command code = 0fh on receiving the completion() command, an sri512 in selected state switches to deactivated state and stops decoding any new commands. the sri512 is then locked in this state until a complete reset (tag out of the field range). a new sri512 can thus be accessed through a select() command without having to remove the previous one from the field. the completion() command does not generate a response. all sri512 devices not in selected state ignore the completion() command. figure 35. completion request format request parameters: no parameter figure 36. completion response format figure 37. completion frame exchange between reader and sri512 sof completion crc l crc h eof ai07679b 0fh 8 bits 8 bits ai07680 no response sof 0fh crc l crc h eof ai10646 reader sri512 no response
sri512 commands sri512 34/47 doc id 13263 rev 5 8.6 reset_to_inventory() command command code = 0ch on receiving the reset_to_inventory() command, all sri512 devices in selected state revert to inventory state. the concerned sri512 devices are thus resubmitted to the anticollision sequence. this comm and is useful when two sri 512 devices with the same 8- bit chip_id happen to be in selected state at the same time. forcing them to go through the anticollision sequence again allows the rea der to generates new pcall16() co mmands and so, to set new random chip_ids. the reset_to_inventory() command does not generate a response. all sri512 devices that are not in selected state ignore the reset_to_inventory() command. figure 38. reset_to_inventory request format request parameter: no parameter figure 39. reset_to_inventory response format figure 40. reset_to_inventory frame exchange between reader and sri512 sof reset_to_inventory crc l crc h eof ai07682b 0ch 8 bits 8 bits ai07680 no response sof 0ch crc l crc h eof ai10947 reader sri512 no response
sri512 sri512 commands doc id 13263 rev 5 35/47 8.7 read_block(addr) command command code = 08h on receiving the read_block command, the sri512 reads the desired block and returns the 4 data bytes contained in the block. data bytes are transmitted with the least significant byte first and each byte is transmitt ed with the least significant bit first. the address byte gives access to the 16 blocks of the sri512 (addresses 0 to 15). read_block commands issued with a block addre ss above 15 will not be interpreted and the sri512 will not return any response, except fo r the system area lo cated at address 255. the sri512 must have received a select() command and be switched to selected state before any read_block() command can be accepted. all read_block() commands sent to the sri512 before a select() command is issued are ignored. figure 41. read_block request format request parameter: address: block addresses from 0 to 15, or 255 figure 42. read_block response format response parameters: data 1: less significant data byte data 2: data byte data 3: data byte data 4: most significant data byte figure 43. read_block frame exchange between reader and sri512 sof read_block crc l crc h eof ai07684b 08h 8 bits 8 bits 8 bits address sof data 1 crc l crc h eof ai07685b 8 bits data 2 data 3 data 4 8 bits 8 bits 8 bits 8 bits 8 bits s of d a t a 1 ai1094 8 c d a t a 2d a t a 3 d a t a 4 re a der s ri512 crc l crc h eof <-t 0 -> <-t 1 -> s of 0 8 h crc l crc h eof addre ss
sri512 commands sri512 36/47 doc id 13263 rev 5 8.8 write_block (addr, data) command command code = 09h on receiving the write_block command, the sri512 writes the 4 bytes contained in the command to the addressed block, provided that the block is available and not write- protected. data bytes are transmitted with the least significant byte first, and each byte is transmitted with the least significant bit first. the address byte gives access to the 16 blocks of the sri512 (addresses 0 to 15). write_block commands issued with a block addr ess above 15 will not be interpreted and the sri512 will not return any response, except fo r the system area lo cated at address 255. the result of the write_block command is submitted to the addressed block. see the following paragraphs for a complete description of the write_block command: figure 12: resettable otp area (addresses 0 to 4) . figure 15: binary counter (addresses 5 to 6) . figure 17: eeprom (addresses 7 to 15) . the write_block command does not give rise to a response from the sri512. the reader must check after the programming time, t w , that the data was correctly programmed. the sri512 must have received a select() command and be switched to selected state before any write_block command can be accepted. all write_block commands sent to the sri512 before a select() command is issued, are ignored. figure 44. write_block request format request parameters: address: block addresses from 0 to 15, or 255 data 1: less significant data byte data 2: data byte data 3: data byte data 4: most significant data byte. figure 45. write_block response format sof data 1 crc l crc h eof ai07687b 8 bits data 2 data 3 data 4 8 bits 8 bits 8 bits 8 bits 8 bits write_block address 09h 8 bits ai07680 no response
sri512 sri512 commands doc id 13263 rev 5 37/47 figure 46. write_block frame exchange between reader and sri512 8.9 get_uid() command command code = 0bh on receiving the get_uid command, the sri512 returns its 8 uid bytes. uid bytes are transmitted with the least significant byte first, and each byte is transmitted with the least significant bit first. the sri512 must have received a select() command and be switched to selected state before any get_uid() command can be accepted. all get_uid() commands sent to the sri512 before a select() command is issued, are ignored. figure 47. get_uid request format request parameter: no parameter figure 48. get_uid response format response parameters: uid 0: less significant uid byte uid 1 to uid 6: uid bytes uid 7: most significant uid byte. data 1 ai10949b data 2 data 3 data 4 reader sri512 crc l crc h eof sof 09h address no response sof get_uid crc l crc h eof ai07693b 0bh 8 bits 8 bits sof uid 1 crc l crc h eof ai07694 8 bits uid 2 uid 3 uid 4 8 bits 8 bits 8 bits 8 bits 8 bits uid 0 uid 5 8 bits uid 6 8 bits 8 bits uid 7 8 bits
sri512 commands sri512 38/47 doc id 13263 rev 5 unique identifier (uid) members of the sri512 family are uniquely identified by a 64-bit unique identifier (uid). this is used for addressing each sri512 de vice uniquely after the anticollision loop. the uid complies with iso/iec 15963 and iso/iec 7816-6. it is a read-only code, and comprises (as summarized in figure 49 ): an 8-bit prefix, with the most significant bits set to d0h an 8-bit ic manufacturer code (iso/iec 7816-6/am1) set to 02h (for stmicroelectronics) a 6-bit ic code set to 00 0110b = 6d for sri512 a 42-bit unique serial number figure 49. 64-bit unique identifier of the sri512 figure 50. get_uid frame exchange between reader and sri512 8.10 power-on state after power-on, the sri512 is in the following state: it is in the low-power state. it is in ready state. it shows highest impedance with respect to the reader antenna field. it will not respond to any co mmand except initiate(). ai12375 d0h unique serial number 02h 63 55 47 0 most significant bits least significant bits 41 6d s o f crc l crc h e o f ai10950 reader sri512 <-t 0 -> <-t 1 -> s o f crc l crc h e o f 0bh uid 1 uid 2 uid 3 uid 4 uid 0 uid 5 uid 6 uid 7
sri512 maximum rating doc id 13263 rev 5 39/47 9 maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 6. absolute maximum ratings symbol parameter min. max. unit t stg t stg storage conditions wafer (kept in its antistatic bag) 15 25 c 23 months i cc supply current on ac0 / ac1 ?20 20 ma v max input voltage on ac0 / ac1 ?7 7 v v esd electrostatic discharge voltage machine model (1) 1. mil. std. 883 - method 3015 ?100 100 v human body model (1) ?1000 1000 v
dc and ac parameters sri512 40/47 doc id 13263 rev 5 10 dc and ac parameters table 7. operating conditions symbol parameter min. max. unit t a ambient operating temperature ?20 85 c table 8. dc characteristics symbol parameter condition min typ max unit v cc regulated voltage 2.5 3.5 v i cc supply current (active in read) v cc = 3.0 v 100 a i cc supply current (active in write) v cc = 3.0 v 250 a v ret backscattering-induced voltage iso 10373-6 20 mv c tun internal tuning capacitor 13.56 mhz 64 pf table 9. ac characteristics (1) 1. all timing measurements were performed on a reference antenna with the following characteristics: external size: 75 mm x 48 mm number of turns: 3 width of conductor: 1 mm space between 2 conductors: 0.4 mm value of the coil: 1.4 h tuning frequency: 14.4 mhz. symbol parameter condition min max unit f cc external rf signal frequency 13.553 13.567 mhz mi carrier carrier modulation index mi=(a-b)/(a+b) 8 14 % t rfr ,t rff 10% rise and fall times 0.8 2.5 s t rfsbl minimum pulse width for start bit etu = 128/f cc 9.44 s t jit ask modulation data jitter coupler to sri512 ?2 +2 s t min cd minimum time from carrier generation to first data 5ms f s subcarrier frequency f cc /16 847.5 khz t 0 antenna reversal delay 128/f s 151 s t 1 synchronization delay 128/f s 151 s t 2 answer to new request delay 14 etu 132 s t dr time between request characters coupler to sri512 0 57 s t da time between answer characters sri512 to coupler 0 s t w programming time for write with no auto-erase cycle (otp) 3ms with auto-erase cycle (eeprom) 5ms binary counter decrement 7 ms
sri512 dc and ac parameters doc id 13263 rev 5 41/47 figure 51. sri512 synchronous timing, transmit and receive ab t rff t rfr t rfsbl t min cd ? cc ask modulated signal from the reader to the contactless device data 0 eof 847khz t dr t 0 t 1 frame transmission between the reader and the contactless device frame transmitted by the reader in ask frame transmitted by the sri512 1 1 t dr in bpsk data 0 1 data 0 t da t da sof 1 0 1 1 start 0 t rfsbl t rfsbl t rfsbl t jit t jit t jit t jit t jit t rfsbl t rfsbl data jitter on frame transmitted by the reader in ask ai10951
part numbering sri512 42/47 doc id 13263 rev 5 11 part numbering note: devices are shipped from the factory with the memory content bits erased to 1. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest st sales office. table 10. ordering information scheme example: sri512 ? w4 / 1ge device type sri512 package w4 = 180 m 15 m unsawn wafer sbn18 = 180 m 15 m bumped and sawn wafer on 8-inch frame customer code 1ge = generic product xxx = customer code after personalization
sri512 iso 14443 type b crc calculation doc id 13263 rev 5 43/47 appendix a iso 14443 type b crc calculation #include #include #include #include #define byte unsigned char #define ushort unsigned short unsigned short updatecrc(byte ch, ushort *lpwcrc) { ch = (ch^(byte)((*lpwcrc) & 0x00ff)); ch = (ch^(ch<<4)); *lpwcrc = (*lpwcrc >> 8)^((ushort)ch << 8)^((ushort)ch<<3)^((ushort)ch>>4); return(*lpwcrc); } void computecrc(char *data, int length, byte *transmitfirst, byte *transmitsecond) { byte chblock; ushortt wcrc; wcrc = 0xffff; // iso 3309 do { chblock = *data++; updatecrc(chblock, &wcrc); } while (--length); wcrc = ~wcrc; // iso 3309 *transmitfirst = (byte) (wcrc & 0xff); *transmitsecond = (byte) ((wcrc >> 8) & 0xff); return; } int main(void) { byte buffcrc_b[10] = {0x0a, 0x12, 0x34, 0x56}, first, second, i; printf("crc-16 g(x) = x^16 + x^12 + x^5 + 1?); printf("crc_b of [ "); for(i=0; i<4; i++) printf("%02x ",buffcrc_b[i]); computecrc(buffcrc_b, 4, &first, &second); printf("] transmitted: %02x then %02x.?, first, second); return(0);
sri512 command brief sri512 44/47 doc id 13263 rev 5 appendix b sri512 command brief figure 52. initiate frame exchange between reader and sri512 figure 53. pcall16 frame exchange between reader and sri512 figure 54. slot_marker frame exchange between reader and sri512 figure 55. select frame exchange between reader and sri512 figure 56. completion frame exchange between reader and sri512 ai10942 reader sri512 sof chip_id crc l crc h eof <-t 0 -> <-t 1 -> sof 06h crc l crc h eof 00h sof 06h crc l crc h eof ai10943 reader sri512 sof chip_id crc l crc h eof <-t 0 -> <-t 1 -> 04h sof x6h crc l crc h eof ai10944 reader sri512 sof chip_id crc l crc h eof <-t 0 -> <-t 1 -> ai10945 reader sri512 sof chip_id crc l crc h eof <-t 0 -> <-t 1 -> sof 0eh crc l crc h eof chip_id sof 0fh crc l crc h eof ai10646 reader sri512 no response
sri512 sri512 command brief doc id 13263 rev 5 45/47 figure 57. reset_to_inventory frame exchange between reader and sri512 figure 58. read_block frame exchange between reader and sri512 figure 59. write_block frame exchange between reader and sri512 figure 60. get_uid frame exchange between reader and sri512 sof 0ch crc l crc h eof ai10947 reader sri512 no response s of d a t a 1 ai1094 8 c d a t a 2d a t a 3 d a t a 4 re a der s ri512 crc l crc h eof <-t 0 -> <-t 1 -> s of 0 8 h crc l crc h eof addre ss data 1 ai10949b data 2 data 3 data 4 reader sri512 crc l crc h eof sof 09h address no response s o f crc l crc h e o f ai10950 reader sri512 <-t 0 -> <-t 1 -> s o f crc l crc h e o f 0bh uid 1 uid 2 uid 3 uid 4 uid 0 uid 5 uid 6 uid 7
revision history sri512 46/47 doc id 13263 rev 5 revision history table 11. document revision history date revision changes 10-apr-2006 1 initial release. 31-oct-2006 2 document status promot ed from target specification to preliminary data. the resettable otp area can no longer be optionally set as a lockable eeprom area. refer ences to the otp_config_bit removed, this bit is always at ?0?. v ret and c tun added to table 8: dc characteristics . 05-apr-2007 3 document status promot ed from preliminary data to full datasheet. c tun min and max values removed, typical value added in ta bl e 8 : dc characteristics . small text changes. all antennas are ecopack? compliant. 28-aug-2008 4 sri512 products are no longer delivered with a3, a4 and a5 antennas. table 6: absolute maximum ratings and ta bl e 1 0 : ordering information scheme clarified. small text changes. 28-jul-2009 5 initial counter values corrected in section 4.2: 32-bit binary counters .
sri512 doc id 13263 rev 5 47/47 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2009 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of SRI512-A5T1GE

	To Download SRI512-A5T1GE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .